Non-volatile memory devices include memory cells that have at least two stable states. In some non-volatile memory devices, each state has a different resistance characteristic such that the resistance through the memory cell differs based on the state of the memory cell. The resistance through the memory cell is higher in one state relative to the resistance through the memory cell in another state. These memory devices can be reprogrammable or one-time programmable devices.
One type of reprogrammable non-volatile memory known in the art relies on magnetic memory cells. These devices, known as magnetic random access memory (MRAM) devices, include an array of magnetic memory cells. The magnetic memory cells may be of different types. For example, a magnetic tunnel junction (MTJ) memory cell or a giant magnetoresistive (GMR) memory cell.
Generally, the magnetic memory cell includes a layer of magnetic film in which the orientation of magnetization is alterable and a layer of magnetic film in which the orientation of magnetization may be fixed or “pinned” in a particular direction. The magnetic film having alterable magnetization is referred to as a sense layer or data storage layer and the magnetic film that is fixed is referred to as a reference layer or pinned layer. In an MTJ memory cell, a barrier layer separates the sense layer and the reference layer.
Conductive traces referred to as word lines and bit lines are routed across the array of memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. A memory cell stores a bit of information as an orientation of magnetization in a sense layer at each intersection of a word line and a bit line. The orientation of magnetization in the sense layer aligns along an axis of the sense layer referred to as its easy axis. The orientation of magnetization does not easily align along an axis orthogonal to the easy axis, referred to as the hard axis. Magnetic fields are applied to flip the orientation of magnetization in the sense layer along its easy axis to either a parallel or anti-parallel orientation with respect to the orientation of magnetization in the reference layer.
In one configuration, the word lines and bit lines are routed across the array of memory cells to aid in flipping the orientation of magnetization in sense layers. The bit lines extend along columns of memory cells near the reference layers. The word lines extend along rows of memory cells near the sense layers. The word lines and bit lines are electrically coupled to a write circuit.
During a write operation, the write circuit selects one word line and one bit line to change the orientation of magnetization in the sense layer of the memory cell situated at the conductors crossing point. The write circuit supplies write currents to the selected word line and bit line to create magnetic fields in the selected memory cell. These write currents may be the same or different in magnitude. The magnetic fields combine to switch the orientation of magnetization in the selected memory cell from parallel to anti-parallel or vice-versa.
The resistance through a memory cell differs according to the parallel or anti-parallel orientation of magnetization of the sense layer and the reference layer. The resistance is highest when the orientation is anti-parallel, which can be referred to as the logic “1” state, and lowest when the orientation is parallel, which can be referred to as the logic “0” state. The resistive state of the memory cell can be determined by sensing the resistance through the memory cell.
Word lines and bit lines aid in sensing the resistance through a memory cell. Word lines, which extend along rows, are electrically coupled to sense layers, and bit lines, which extend along columns, are electrically coupled to reference layers. Word lines and bit lines are also electrically coupled to a read circuit.
During a read operation, the read circuit selects one word line and one bit line to sense the resistance of the memory cell situated at the conductors crossing point. The read circuit can supply a voltage across the selected memory cell and provide a sense current through the memory cell. The sense current is proportional to the resistance through the memory cell. In one configuration, the sense current is compared to a reference current to determine the state of the memory cell. The reference current is used to differentiate a high resistive state from a low resistive state.
Although generally reliable, failures can occur that affect the ability of the memory device to store data reliably. These failures include memory cell failures and sensing failures related to the read circuits. Memory cell failures and sensing failures can result from causes including manufacturing imperfections, process variations and aging of the memory device.
The memory device is tested to determine whether the read circuits and memory cells are functioning properly. The read circuits can be tested using memory cells as test resistance values. However, memory cells are not always adequate for testing read circuits.
The resistance through a memory cell differs from cell to cell in the same array and from memory device to memory device. In an MTJ memory cell, the resistance through the memory cell is dependent on the barrier layer thickness. The barrier layer is a very thin insulating layer between the sense layer and the reference layer. The barrier layer may be aluminum oxide and angstroms thick. The resistance of the memory cell varies exponentially with the thickness of the barrier layer. A change in barrier layer thickness of only 2% can change the resistance through the memory cell by a factor of 2. Even with tight controls, the resistance through memory cells can differ greatly from cell to cell and from memory device to memory device. For this reason, memory cells do not consistently provide adequate test resistance values.